Start-up circuit

ABSTRACT

A start-up circuit includes a power supply node which receives a power supply voltage, a ground node which receives a ground voltage, a first node, a first capacitor which is coupled between the first node and the ground node, a supply circuit which is coupled between the power supply node and the first node, and which supplies an electrical charge from the power supply node to the first capacitor, a discharge circuit which is coupled between the first node and the ground node, and which discharges an electrical charge stored in the first capacitor to the ground node, and an output circuit which is connected to the first node, and which outputs a start-up signal when a voltage level of the first node becomes higher than a set voltage level.

CROSS REFERENCE TO RELATED APPLICATION

[0001] The present application claims priority under 35 U.S.C. § 119 toJapanese Patent Application No. 2001-293892, filed Sep. 26, 2001, whichis herein incorporated by reference in its entirely for all purposes.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a start-up circuit, and moreparticularly to a start-up circuit generating and outputting aninitialization signal which initializes an internal circuit of asemiconductor integrated circuit when a power supply voltage is suppliedto the internal circuit.

[0004] 2. Description of the Related Art

[0005]FIG. 5 is a circuit diagram showing a conventional start-upcircuit 500. The conventional start-up circuit 500 includes a powersupply node T1 to which is a power supply voltage VCC, a ground node T2to which a ground voltage GND, a node n1, a PMOS transistor 501 locatedbetween the power supply node T1 and the node n1, a condenser C51located between the node n1 and the ground node T2, an inverter INV1having PMOS and NMOS transistors 503 and 505, an inverter INV2 havingPMOS and NMOS transistors 507 and 509, and an output node ST. Theinverter INV1 is located between the power supply and ground nodes T1and T2, and receives a signal from the node n1. The inverter INV2 islocated between the power supply and ground nodes T1 and T2, andreceives an output signal of the inverter INV1.

[0006] Charging of the condenser C51 starts when the power supplyvoltage VCC is supplied to the power supply node T1. Then, a voltagelevel of the node n1 rises in response to a time constant on the basisof an ON state resistance of the PMOS transistor 501 and a capacity ofthe condenser C51. Since a charged voltage level of the condenser C51 islow right after the power supply voltage VCC is supplied to the powersupply node T1, the voltage level of the node n1 is initially a low(“L”) level. As a result, since the PMOS transistor 503 assumes an ONstate and the NMOS 505 assumes an OFF state, an output signal of theinverter INV1 is a high (“H”) level. Therefore, the PMOS transistor 507of the inverter INV2 assumes an OFF state and the NMOS transistor 509assumes an ON state, and then an “L” level signal is outputted from theoutput node ST. Then, the condenser C51 is further charged. A “H” levelsignal is eventually outputted from the output node ST after the voltagelevel of the node n1 becomes higher than a threshold voltage level ofthe inverter INV1.

[0007] Accordingly, after the power supply voltage VCC is supplied tothe power supply node T1, the voltage level of the output node ST ismaintained at an “L” level for a certain period in response to the timeconstant, and is then switched to an “H” level after the certain period.An initialization of an internal circuit which is connected to theoutput node ST is performed during the certain period that the voltagelevel of the output node ST is at the “L” level.

[0008] An electrical charge stored in the condenser C51 discharges tothe power supply node T1 through the PMOS transistor 501, when a supplyof the power supply voltage VCC to the power supply node T1 is(interrupted) stopped.

[0009] However, during a discharge of the condenser C51 of theconventional start-up circuit, since the PMOS transistor 501 switches toan off state when a voltage level of the node n1 falls to a thresholdvoltage level of the PMOS transistor 501, an electrical charge havingthe threshold voltage level of the PMOS transistor 501 is still held inthe condenser C51. Such an electrical charge discharges during a statein which the power supply voltage VCC is disrupted. However, adischarging time of the electrical charge becomes to longer. Also, sincethe electrical charge stored in the condenser C51 does not dischargequickly when the power supply voltage VCC is disrupted, an electricalpotential is held at the node n1. Then, if a supply of the power supplyvoltage VCC is resumed, the voltage level of the node n1 exceeds thethreshold voltage level of the inverter INV1 before initialization ofthe internal circuit. As a result, an “H” level signal is outputted fromthe output node ST before the internal circuit can be initializedproperly.

SUMMARY OF THE INVENTION

[0010] The present invention is therefore directed to providing astart-up circuit which substantially overcomes one or more of theproblems due to the limitations and disadvantages of the related art.

[0011] It is an objective of the invention to provide a start-upcircuit, in which a power supply node which receives a power supplyvoltage, a ground node which receives a ground voltage, a first node, afirst capacitor which is located between the first node and the groundnode, a supply circuit which is located between the power supply nodeand the first node, and which supplies an electrical charge from thepower supply node to the first capacitor, a discharge circuit which islocated between the first node and the ground node, and which dischargesan electrical charge stored in the first capacitor to the ground node,and an output circuit which is connected to the first node, and whichoutputs a start-up signal when a voltage level of the first node becomeshigher than a set voltage level.

[0012] According to the present invention, even though the supply of thepower supply voltage to the power supply node is disrupted, a period ofcharging the electrical charge into the condenser can be sufficientlysecured. Therefore, a period of initializing the internal circuitelectrically connected to the output node ST can be sufficientlysecured.

[0013] The present invention can shorten the recovery period from therelease of the disruption of the supply of the power supply voltage,until the termination of the reset signal. Therefore, the presentinvention can achieve a reduction in power consumption of the integratedcircuit.

[0014] The above and further objects and novel features of the inventionwill become more fully apparent from the following detailed description,appended claims and accompanying drawings herein.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] While the specification concludes with claims particularlypointing out and distinctly claiming the subject matter which isregarded as the invention, it is believed that the invention, theobjects and features of the invention and further objects, features andadvantages thereof will be better understood from the followingdescription taken in connection with the accompanying drawings in which:

[0016]FIG. 1 is a block diagram showing a relevant part of a start-upcircuit according to a preferred embodiment of the present invention;

[0017]FIG. 2 is a whole circuit diagram of the start-up circuitaccording to the preferred embodiment of the present invention;

[0018]FIG. 3 is a voltage waveform showing voltage levels of variousnodes when an electrical charge is charged into a condenser of thestart-up circuit according to the preferred embodiment of the presentinvention;

[0019]FIG. 4 is a voltage waveform showing voltage levels of variousnodes when the electrical charge is discharged from the condenser of thestart-up circuit according to the preferred embodiment of the presentinvention; and

[0020]FIG. 5 is a circuit diagram of a conventional power savingintegrated circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Preferred embodiments of the present invention will hereinafterbe described in detail with reference to the accompanying drawings. Thedrawings used for this description typically illustrate majorcharacteristic parts to facilitate understanding of the invention.

[0022]FIG. 1 is a block diagram showing a relevant part of a start-upcircuit 100 according to a preferred embodiment of the presentinvention. As shown in FIG. 1, the start-up circuit 100 includes a powersupply node T1 to which is applied a power supply voltage VCC, a groundnode T2 to which is applied a ground voltage GND, nodes n1 and n2, acondenser C11 which is located between the node n1 and the ground nodeT2 and which is charged by an electrical charge from the power supplynode T1, a condenser C13 which is located between the power supply nodeT1 and the node n2 and which reduces a voltage level of the node n2 whena supply of the power supply voltage VCC to the power supply node T1 isstopped, a charge and discharge circuit (supply circuit) 101 whichdischarges the electrical charge stored in the condenser C11 in responseto a falling of the node n2 when the supply of the power supply voltageto the power supply node T1 is stopped and which supplies the electricalcharge from the power supply node T1 to the condenser C11 when the powersupply voltage VCC is supplied to the power supply node T1, and adischarge circuit 103 which is located between the node n1 and theground node T2 and which discharges the electrical charge stored in thecondenser C11 to the ground node T2 during a set period after the supplyof the power supply voltage VCC to the power supply node T1 is started.The node n1 is electrically connected to an output circuit which outputsan output signal when a voltage level of the node n1 exceeds a setvoltage level after the set period.

[0023]FIG. 2 is a whole circuit diagram of the start-up circuitaccording to the preferred embodiment of the present invention. As shownin FIG. 2, the start-up circuit 100 further includes a PMOS transistors201, a node n5, a PMOS transistor 203, a node n6 and an NMOS transistor205 which are located between the power supply node T1 and the groundnode T2 in series, and which control the amount of a current flowing inthe start-up circuit 100. The start-up circuit 100 shown in FIG. 2includes an output circuit 207 electrically connected to the node n1,and which outputs the output signal when a voltage level of the node n1exceeds a set voltage level after the set period.

[0024] The PMOS transistor 201 is located between the power supply nodeT1 and the node n5, and has control gate and first (source) electrodeswhich are electrically connected to the node n5 and a second (drain)electrode which is electrically connected to the power supply node T1.The PMOS transistor 203 is located between the nodes n5 and n6, and hasa control gate electrode which is electrically connected to the groundnode T2, a first (source) electrode which is electrically connected tothe node n5, and a second (drain) electrode which is electricallyconnected to the node n6. The NMOS transistor 205 is located between thenode n6 and the ground node T2, and has a first electrode which iselectrically connected to the ground node T2, and control gate and first(drain) which are electrically connected to the node n6. PMOStransistors 201 and 203 and NMOS transistor 205 assume an ON state whena voltage level of the power supply node T1 rises due to a supply of thepower supply voltage VCC to the power supply node T1. As a result, aminute current flows between the power supply and ground nodes T1 andT2. Therefore, voltage levels of the nodes n5 and n6 are fixed,respectively.

[0025] The charge and discharge circuit (supply circuit) 101 includes aPMOS transistor 209 having a control gate electrode which iselectrically connected to the node n2, a first (source) electrode whichis electrically connected to power supply node T1, and a second (drain)electrode which is electrically connected to the node n1. ON and OFFstates of the PMOS transistor 209 are determined in accordance with avoltage level of the node n2.

[0026] The condenser C11 is, for example, an NMOS capacitor. Thecondenser C11 is charged with an electrical voltage from the powersupply node T1 after the power supply voltage VCC is supplied from thepower supply node T1 through the PMOS transistor 209. Then, the PMOStransistor 209 is an ON state. A charging speed of the condenser C11 isdetermined in accordance with a time constant, based on a capacity ofthe condenser C11 and an ON state resistance of the PMOS transistor 209.

[0027] The discharge circuit 103 includes a node n3, a condenser C21which is located between the power supply node T1 and the node n3 andwhich rises to a voltage level of the node n3 when a supply of the powersupply voltage VCC to the power supply node T1 is started, a node n4, areduction circuit 213 which is located between the node n3 and theground node T2 and which reduces a voltage level of the node n3 inresponse to a voltage level of the node n4, and a switch circuit 211which is located between the node n1 and the ground node T2 and whichswitches on in response to a rising of the voltage level of the node n3and switches off in response to a falling of the voltage at the node n3.

[0028] The condenser C21 is, for example, a PMOS capacitor. The switchcircuit 211 includes an NMOS transistor 215 having a control gateelectrode which is electrically connected to the node n3, a first(source) electrode which is connected to the ground node T2, and asecond (drain) electrode which is electrically connected to the node n1.The reduction circuit 213 includes an NMOS transistor 217 having acontrol gate electrode which is electrically connected to the node n4, afirst (source) electrode which is electrically connected to the groundnode T2, and a second (drain) electrode which is electrically connectedto the node n3.

[0029] The output circuit 207 includes a node n7, an inverter INV1 whichoutputs a reversal signal to the node n7 in response to the voltagelevel of the node n1, an NMOS transistor 223 which is located betweenthe inverter INV1 and the ground node T2 and which decides a drivingcapacity of the inverter INV1, a condenser C23 which is located betweenthe power supply node T1 and the node n7 and which raises a voltagelevel of the node n7 when the supply of the power supply voltage VCC tothe power supply node T1 is started, an inverter INV2 which outputs areversal signal in response to the voltage level of the node n7, and anoutput node ST which outputs a start-up signal to an internal circuit.

[0030] The inverter INV1 includes PMOS and NMOS transistors 219 and 221.The PMOS transistor 219 has a control gate electrode which iselectrically connected to the node n1, a first (source) electrode whichis electrically connected to the power supply node T1, and a second(drain) electrode which is electrically connected to the node n7. TheNMOS transistor 221 has a control gate electrode which is electricallyconnected to the node n1, a first (source) electrode which iselectrically connected to a source electrode of the NMOS transistor 223,and a second (drain) electrode which is electrically connected to thenode n7. The NMOS transistor 223 has a control gate electrode which iselectrically connected to the node n4, a first (source) electrode whichis electrically connected to the ground node T2, and a second (drain)electrode which is electrically connected to the source electrode of theNMOS transistor 221.

[0031] The PMOS transistors 201 and 203 and NMOS transistor 205 controlthe amount of a current flowing in the start-up circuit 100.Specifically, the transistors 201, 203 and 205 control the amount of thecurrent flowing in the PMOS transistor 209 and the NMOS transistor 223.The voltage level of the node n4 when the power supply voltage VCC issupplied to the power supply node T1, is decided on the basis of an ONresistance of the transistors 201, 203 and 205.

[0032] The PMOS transistor 201 and the PMOS transistor 209 form acurrent mirror. The NMOS transistor 205 and the NMOS transistor 223 forma current mirror. In the preferred embodiment, dimensions of the PMOStransistors 201 and 209 are set such that the same amount of currentflows in the PMOS transistors 201 and 209 when the power supply voltageVCC is supplied to the power supply node T1. A dimension of the PMOStransistor 203 is set such that a minute current flows in the PMOS andNMOS transistors 201 and 205 when the PMOS and NMOS transistors 201 and205 are in an ON state. Dimensions of the NMOS transistors-205 and 223are set such that the same amount of current flow in the NMOStransistors 205 and 223 when the power supply voltage VCC is supplied tothe power supply node T1. As a result, since a minute current flows inthe PMOS transistor 201 when the power supply voltage VCC is supplied tothe power supply node T1, a minute current also flows in the PMOStransistor 209. Therefore, since a minute current flows into the noden1, a charge period of the condenser C11 can be sufficiently secured.

[0033] As mentioned above, the NMOS transistor 223 and the NMOStransistor 205 form a current mirror. As a result, since a minutecurrent flows in the NMOS transistor 205 when the power supply voltageVCC is supplied to the power supply node T1, a minute current flows inthe NMOS transistor 223. Therefore, since a minute current flows in theNMOS transistor 221 when the voltage level of the node n1 exceeds theset voltage level, a desired period required for the voltage level ofthe node n7 to reach a low “L” level can be secured. Specifically, adesired period until the start-up signal (high “H” level signal) isoutputted from the output node ST can be sufficiently secured.

[0034] The condenser C23 is, for example, a PMOS capacitor. Thecondenser C23 rises the voltage level of the node n7 when the supply ofthe power supply voltage VCC to the power supply node T1 is started. Theinternal circuit electrically connected to the output node ST isinitialized during a period until the start-up signal (“H” level signal)is outputted from the output node ST.

[0035]FIG. 3 is a voltage wave form showing voltage levels of variousnodes when an electrical charge is charged into the condenser C11 of thestart-up circuit 100, according to the preferred embodiment of thepresent invention. Specifically, FIG. 3 shows voltage waveforms of thepower supply node T1, the nodes n1 through n7, and the output node ST.FIG. 3 shows a relationship between an electrical change of the variousnodes (along a vertical axis) and time (along a horizontal axis).

[0036] At first, all voltage levels of the nodes n1 through n7 and theoutput node ST, are at the ground voltage GND level before the powersupply voltage VCC is supplied to the power supply node T1.

[0037] At a time t0, the voltage level of the power supply node T1 riseswhen the power supply of the power supply voltage VCC to the powersupply node T1 is started, and the PMOS transistor 201 becomes an ONstate, and the voltage level of the node n5 rises. Next, the PMOStransistor 203 switches to an ON state in response to the voltage levelof the node n5, and the voltage level of the node n6 rises, and the NMOStransistor 205 switches to an ON state in response to the voltage levelof the node n6. As a result, since a minute current flows between thepower supply node T1 and the ground node T2 through the transistors 201,203 and 205, the voltage levels of the nodes n5 and n6 are fixed,respectively. The voltage level of the node n5 is“VCC-Vt_((PMOS209))-α”, and the voltage level of the node n6 is“Vt_((NMOS217))+α”. The voltage level “VCC-Vt_((PMOS209))-α” indicatesthat the voltage level between source and drain of the PMOS transistor209 is higher than “a power supply voltage VCC-a threshold voltageVt_((PMOS209)) of the PMOS transistor 209”. The “Vt_((NMOS217))+α”indicates that the voltage level between source and drain of the NMOStransistor 215 is higher than “a threshold voltage Vt_((NMOS217)) of thePMOS transistor 209”. As a result, a current flowing in the transistors201, 203 and 205 can be reduced as possible. The “α” is, for example,one or a few tenths of a volt.

[0038] The voltage level of the node n3 rises due to the condenser C21,in accordance with following a rising of the power supply node T1. Thevoltage level of the node n7 rises due to the condenser C23, inaccordance with following a rising of the power supply node T1.

[0039] At a time t1, an electrical charge flows into the node n1 throughthe PMOS transistor 209 when the voltage level of the node n5 reachesthe level “VCC-Vt_((PMOS209))-α”, and the electrical charge starts tocharge into the condenser C1. Since the electrical charge is chargedinto the condenser C11, the voltage level of the node n1 starts to rise.As noted above, the PMOS transistor 209 and the PMOS transistor 201 forma current mirror. Since the same amount of the minute current flows inthe PMOS transistors 201 and 209, the voltage level of the node n1 risesgently. As a result, a period until the start-up signal (“H” levelsignal) is outputted from the output node ST can be sufficientlysecured. Therefore, a period of initializing the internal circuit can besufficiently secured.

[0040] The voltage level of the node n4 electrically connected to thenode n6 becomes “Vt_((NMOS217))+α”, and as a result, the NMOS transistor217 switches to an ON state. The voltage level of the node n3 which roseup the power supply voltage VCC level, falls to the ground voltage GNDlevel. The NMOS transistor 215 switches to an OFF state in response to afalling of the node n3, and as a result, the node n1 and the ground nodeT2 are electrically disconnected during electrical charging of thecondenser C11.

[0041] At a time t2, the PMOS transistor 219 switches to an OFF stateand the NMOS transistor 221 switches to an ON state, when the voltagelevel of the node n1 exceeds a set voltage level (in response to arising of the node n1). The NMOS transistor 223 is an ON state due tothe voltage level “Vt_((NMOS217))+α” of the node n4. Therefore, sincethe electrical charge of the node n7 flows to the ground node T2 throughthe NMOS transistors 221 and 223, the voltage level of the node n7starts to fall. As noted above, the NMOS transistor 223 and the NMOStransistor 205 form a current mirror. Since the same amount of theminute current flow in the NMOS transistors 205 and 223, the voltagelevel of the node n7 falls gently. As a result, a period until thestart-up signal (“H” level signal) is outputted from the output node STcan be sufficiently secured. Therefore, a period of initializing theinternal circuit can be sufficiently secured.

[0042] At a time t3, the inverter INV2 begins to raise the voltage levelof the output node ST, whereby the output node ST subsequently outputsthe start-up signal (“H” level signal) to the internal circuit.

[0043] The voltage level of the output node ST keeps “L” level during aset period, and then changes to “H” level. The internal circuit isinitialized during the period when the voltage level of the output nodeST is “L” level. In order words, the internal circuit is initializedduring a period from a beginning of the supply of the power supplyvoltage VCC to the power supply node T1, to an outputting of thestart-up signal.

[0044]FIG. 4 is a voltage wave form showing voltage levels of variousnodes when an electrical charge is discharged from the condenser C11 ofthe start-up circuit 100, in the start-up circuit 100 according to thepreferred embodiment of the present invention. Specifically, FIG. 4shows voltage waveform of the power supply node T1, the nodes n1 throughn7, and the output node ST. FIG. 4 shows a relationship between anelectrical change of the various nodes (along a vertical axis) and atime (along a horizontal axis).

[0045] At first, all voltage levels of the nodes n2 and n5 are“VCC-Vt_((PMOS209))-α”, and the voltage level of the nodes n4 and n6 are“Vt_((NMOS217))+α”, before the supply of the power supply voltage VCC tothe power supply node T1 is disrupted. Also, the voltage levels of thenode n1 and the output node ST are the power supply voltage VCC level,and the voltage levels of the nodes n3 and n7 are the ground voltage GNDlevel.

[0046] At a time t4, the voltage level of the power supply node T1 fallsto the ground voltage GND level when the supply of the power supplyvoltage VCC to the power supply node T1 is disrupted, and the voltagelevel of the node n2 falls to under the ground voltage GND level. Atthat time, since the condenser C13 operates to keep the electricalcharge, an electrical change of the node n2 is the same an electricalchange of the power supply node T1. Therefore, since the first voltagelevel of the node n2 is “VCC-Vt_((PMOS209))-α”, the voltage level of thenode n2 falls to under the ground voltage GND level in accordance withthe electrical change.

[0047] The PMOS transistor 209 becomes an ON state in response to thevoltage level of the node n2. As a result, the electrical charge storedin the condenser C11 is discharged to the power supply node T1 keepingthe ground voltage GND level, and the voltage level of the node n1falls.

[0048] At a time t5, the voltage level of the power supply node T1starts to rise when the supply of the power supply voltage VCC to thepower supply node T1 is resumed. The voltage of the node n3 rises due tothe condenser C21, in accordance with a rising of the power supply nodeT1. As a result, the NMOS transistor 215 switches to an ON state, andthe node n1 and the ground node T2 are electrically connected.Therefore, the electrical charge remaining in the condenser C11 isdischarged to the ground node T2, and the voltage level of the node n1falls to the ground voltage GND level.

[0049] Next, the voltage level of the node n6 rises, and the voltagelevel of the node n4 which is electrically connected to the node n6rises. As a result, the NMOS transistor 217 switches to an ON state, andthe node n3 and the ground node T2 are electrically connected. Further,the voltage level of the node n3 falls, and the NMOS transistor 215switches to an OFF state.

[0050] According to the preferred embodiment of the present invention,since the start-up circuit 100 includes the condenser C13, the chargeand discharge circuit 101 and the discharge circuit 103, the electricalcharge stored in the condenser C11 can be quickly discharged to thepower supply node T1 when the supply of the power supply voltage VCC tothe power supply node T1 is disrupted. Also, the electrical chargeremaining in the condenser C11 can be quickly discharged to the groundnode T2 when the supply of the power supply voltage VCC to the powersupply node T1 is resumed. As a result, even through the supply of thepower supply voltage VCC to the power supply node T1 is disrupted, aperiod of charging the electrical charge into the condenser C11 can besufficiently secured. Therefore, a period of initializing the internalcircuit electrically connected to the output node ST can be sufficientlysecured.

[0051] As described above, the start-up circuit can quickly dischargethe electrical charge stored in the condenser to the power supply nodewhen the supply of the power supply voltage to the power supply node isdisrupted. Also, the start-up circuit can quickly discharge theelectrical charge remaining in the condenser to the ground node when thesupply of the power supply voltage to the power supply node is resumed.As a result, even through the supply of the power supply voltage to thepower supply node is disrupted, a period of charging the electricalcharge into the condenser can be sufficiently secured. Therefore, aperiod of initializing the internal circuit electrically connected tothe output node ST can be sufficiently secured.

[0052] The present invention has been described with reference toillustrative embodiments, however, this description must not beconsidered to be confined only to the embodiments illustrated. Variousmodifications and changes of these illustrative embodiments and theother embodiments of the present invention will become apparent to oneskilled in the art from reference to the description of the presentinvention. It is therefore contemplated that the appended claims willcover any such modifications or embodiments as fall within the truescope of the invention.

What is claimed is:
 1. A start-up circuit, comprising: a power supplynode which receives a power supply voltage; a ground node which receivesa ground voltage; a first node; a first capacitor which is coupledbetween the first node and the ground node; a supply circuit which iscoupled between the power supply node and the first node, and whichsupplies an electrical charge from the power supply node to the firstcapacitor; a discharge circuit which is coupled between the first nodeand the ground node, and which discharges an electrical charge stored inthe first capacitor to the ground node; and an output circuit which isconnected to the first node, and which outputs a start-up signal when avoltage level of the first node becomes higher than a set voltage level.2. The start-up circuit according to claim 1, further comprising: asecond node which is connected to the power supply node through a secondcapacitor, wherein the supply circuit includes a first transistor havinga control gate electrode which is connected to the second node, a firstelectrode which is connected to the power supply node, and a secondelectrode which is connected to the first node.
 3. A start-up circuit,comprising: a power supply node which receives a power supply voltage; aground node which receives a ground voltage; a first node; a firstcapacitor which is coupled between the first node and the ground node; asupply circuit which is coupled between the power supply node and thefirst node, and which supplies an electrical charge from the powersupply node to the first capacitor; a discharge circuit which is coupledbetween the first node and the ground node, and which discharges anelectrical charge stored in the first capacitor to the ground node, thedischarge circuit a second node, a second capacitor which raises avoltage level of the second node when a supply of the power supplyvoltage to the power supply node is started, and a switch circuit whichelectrically connects the first node and the ground node in response torising of the voltage level of the second node; and an output circuitwhich is connected to the first node, and which outputs a start-upsignal when a voltage level of the first node becomes higher than a setvoltage level.
 4. The start-up circuit according to claim 3, furthercomprising: a third node which is connected to the power supply nodethrough a third capacitor, wherein the supply circuit comprises a firsttransistor having a control gate electrode which is connected to thesecond node, a first electrode which is connected to the power supplynode, and a second electrode which is connected to the first node. 5.The start-up circuit according to claim 3, wherein the switch circuitincludes a transistor having a control gate which is connected to thesecond node, a first electrode which is connected to the ground node,and a second electrode which is connected to the first node.
 6. Astart-up circuit, comprising: a power supply node which receives a powersupply voltage; a ground node which receives a ground voltage; a firstnode; a first capacitor which is coupled between the first node and theground node; a supply circuit which is coupled between the power supplynode and the first node, and which supplies an electrical charge fromthe power supply node to the first capacitor; a discharge circuit whichis coupled between the first node and the ground node, and whichdischarges an electrical charge stored in the first capacitor to theground node during a set period after a supply of the power supplyvoltage to the power supply node is started, the discharge circuithaving a second node, a second capacitor which raises a voltage level ofthe second node when the supply of the power supply voltage to the powersupply node is started, a third node, a reduction circuit which lowersthe voltage level of the second node in response to a voltage level ofthe third node, and a switch circuit which electrically connects betweenthe first node and the ground node in response to rising of the voltagelevel of the second node and electrically disconnects the first node andthe ground node in response to falling of the voltage level of thesecond node; and an output circuit which is connected to the first node,and which outputs a start-up signal when a voltage level of the firstnode becomes higher than a set voltage level.
 7. The start-up circuitaccording to claim 6, further comprising: a fourth node which isconnected to the power supply node through a third capacitor, whereinthe supply circuit includes a first transistor having a control gateelectrode which is connected to the fourth node, a first electrode whichis connected to the power supply node, and a second electrode which isconnected to the first node.
 8. The start-up circuit according to claim6, wherein the switch circuit includes a transistor having a controlgate which is connected to the second node, a first electrode which isconnected to the ground node, and a second electrode which is connectedto the first node.
 9. The start-up circuit according to claim 6, whereinthe reduce circuit includes a transistor having a control gate electrodewhich is connected to the third node, a first electrode which isconnected to the ground node, and a second electrode which is connectedto the second node.
 10. A start-up circuit, comprising: a power supplynode which receives a power supply voltage; a ground node which receivesa ground voltage; a first node; a first capacitor which is coupledbetween the first node and the ground node; a second node; a secondcapacitor which is coupled between the power supply node and the secondnode, and which reduces a voltage level of the second node when a supplyof the power supply voltage to the power supply node is stopped; acharge and discharge circuit which is coupled between the power supplynode and the first node, and which discharges an electrical chargestored in the first capacitor to the power supply node in response tofalling of the voltage level of the second node when the supply of thepower supply voltage to the power supply node is stopped, and whichsupplies the electrical charge from the power supply node to the firstcapacitor when the supply of the power supply voltage to the powersupply node is started; a discharge circuit which is located between thefirst node and the ground node, and wherein the discharge circuitdischarges the electrical charge stored in the first capacitor to theground node during a set period after the supply of the power supplyvoltage to the power supply node is started, the discharge circuithaving a third node, a third capacitor which rises a voltage level ofthe third node when the supply of the power supply voltage to the powersupply node is started, and a switch circuit which electrically connectsbetween the first node and the ground node in response to rising of thevoltage level of the third node; and an output circuit which isconnected to the first node, and which outputs a start-up signal when avoltage level of the first node becomes higher than a set voltage level.11. The start-up circuit according to claim 10, wherein the charge anddischarge circuit includes a first transistor having a control gateelectrode which is connected to the second node, a first electrode whichis connected to the power supply node, and a second electrode which isconnected to the first node.
 12. The start-up circuit according to claim10, wherein the switch circuit includes a second transistor having acontrol gate which is connected to the third node, a first electrodewhich is connected to the ground node, and a second electrode which isconnected to the first node.
 13. A start-up circuit, comprising: a powersupply node which receives a power supply voltage; a ground node whichreceives a ground voltage; a first node; a first capacitor which iscoupled between the first node and the ground node; a second node; asecond capacitor which is coupled between the power supply node and thesecond node, and which reduces a voltage level of the second node when asupply of the power supply voltage to the power supply node is stopped;a charge and discharge circuit which is coupled between the power supplynode and the first node, and which discharges an electrical chargestored in the first capacitor to the power supply node in response tofalling of the voltage level of the second node when the supply of thepower supply voltage to the power supply node is stopped, and whichsupplies the electrical charge from the power supply node to the firstcapacitor when the supply of the power supply voltage to the powersupply node is started; a discharge circuit which is located between thefirst node and the ground node, and wherein the discharge circuitdischarges the electrical charge stored in the first capacitor to theground node during a set period after the supply of the power supplyvoltage to the power supply node is started, and having a third node, athird capacitor which rises a voltage level of the third node when thesupply of the power supply voltage to the power supply node is started,and a switch circuit which electrically connects between the first nodeand the ground node in response to rising of the voltage level of thethird node and electrically disconnects between the first node and theground node in response to a falling of the voltage level of the thirdnode; and an output circuit which is connected to the first node, andwhich outputs a start-up signal when a voltage level of the first nodebecomes higher than a set voltage level.
 14. The start-up circuitaccording to claim 13, wherein the charge and discharge circuit includesa first transistor having a control gate electrode which is connected tothe second node, a first electrode which is connected to the powersupply node, and a second electrode which is connected to the firstnode.
 15. The start-up circuit according to claim 13, wherein the switchcircuit includes a second transistor having a control gate which isconnected to the third node, a first electrode which is connected to theground node, and a second electrode which is connected to the firstnode.